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a49lf040 4 mbit cmos 3.3volt-only lo w pin count flash memory preliminary preliminary (august, 2004, version 0.1) amic technology, corp. document title 4 mbit cmos 3.3 volt-only low pin count flash memory revision history rev. no. history issue date remark 0.0 initial issue february 17, 2004 preliminary 0.1 add pb-free package type august 20, 2004
a49lf040 4 mbit cmos 3.3volt-only lo w pin count flash memory preliminary preliminary (august, 2004, version 0.1) 1 amic technology, corp. features ? single power supply operation - low voltage range: 3.0 v - 3.6 v for read and write operations ? standard intel low pin count interface - read compatible to intel? low pin count (lpc) interface ? memory configuration - 512k x 8 (4 mbit) ? block architecture - 4mbit: eight uniform 64kbyte blocks - supports full chip erase for address/address multiplexed (a/a mux) mode ? automatic erase and program operation - embedded byte program and block/chip erase algorithms - typical 10 s/byte programming time - typical 1s block erase time ? two operational modes - low pin count interface (lpc) mode for in-system operation - address/address multiplexed (a/a mux) interface mode for programming equipment ? low pin count (lpc) mode - 33 mhz synchronous operation with pci bus - 5-signal communication interface for in-system read and write operations - standard sdp command set - data# polling (i/o 7 ) and toggle bit (i/o 6 ) features - 4 id pins for multi-chip selection - 5 gpi pins for general purpose input register - tbl# pin for hardware write protection to boot block - wp# pin for hardware write protection to whole memory array except boot block ? address/address multiplexed (a/a mux) mode - 11-pin multiplexed address and 8-pin data i/o interface - supports fast programming on eprom programmers - standard sdp command set - data# polling (i/o 7 ) and toggle bit (i/o 6 ) features ? lower power consumption - typical 12ma active read current - typical 24ma program/erase current ? high product endurance - guarantee 100,000 program/erase cycles for each block - minimum 20 years data retention ? compatible pin-out and packaging - 32-pin (8 mm x 14 mm) tsop (type i) - 32-pin plcc general description the a49lf040 flash memory device is designed to be read- compatible with the intel low pin count (lpc) interface specification 1.1. this device is designed to use a single low voltage, range from 3.0 volt to 3.6 volt power supply to perform in-system or off-system read and write operations. it provides protection for the st orage and update of code and data in addition to adding system design flexibility through five general-purpose inputs. two interface modes are supported by the a49lf040: low pin count (lpc) interface mode for in-system programming and address/address multiplexed (a/a mux) mode for fast factory programming of pc-bios applications. the memory is divided into eight uniform 64kbyte blocks that can be erased independently wi thout affecting the data in other blocks. blocks also can be protected individually to prevent accidental program or erase commands from modifying the memory. the program and erase operations are executed by issuing the program/erase commands into the command interface by which activating the internal control logic to automatically process the program/erase procedures. the device can be programmed on a byte-by- byte basis after performing the erase operation. in addition to the block erase operation, the ch ip erase feature is provided in a/a mux mode that allows the whole memory to be erased in one single erase operation. the a49lf040 provides the status detection such as data# polling and toggle bit functions in both lpc and a/a mux modes. the process or completion of program and erase operations can be detected by reading the status bits. the a49lf040 is offered in 32-lead tsop and 32-lead plcc packages. see figures 1 and 2 for pin assignments and table 1 for pin descriptions.
a49lf040 preliminary (august, 2004, version 0.1) 2 amic technology, corp. pin configurations a7 (gpi1) a6 (gpi0) a5 (wp#) a4 (tbl#) a3 (id3) a2 (id2) a1 (id1) a0 (id0) i/o 0 (lad0) 21 22 23 24 25 26 27 28 29 12 13 11 8 9 5 7 6 rb# (res) i/o 7 (res) we# (lframe#) 32-lead plcc top view oe# (init#) vdd (vdd) nc nc vss (vss) mode (mode) i/o 1 (lad1) i/o 2 (lad2) vss (vss) i/o 3 (lad3) i/o 4 (res) i/o 5 (res) i/o 6 (res) 4 3 2 1 32 31 30 a8 (gpi2) a9 (gpi3) rst# (rst#) nc vdd (vdd) r/c# (lclk) a10 (gpi4) 14 15 16 17 18 19 20 10 (*) designates lpc mode figure 1: pin assignments for 32-lead plcc 32-lead tsop (8 mm x 14 mm ) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc vss (vss) mode (mode) a10 (gpi4) r/c# (lclk) vdd (vdd) rst# (rst#) a9 (gpi3) a8 (gpi2) a7 (gpi1) a6 (gpi0) a5 (wp#) a4 (tbl#) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a3 (id3) a2 (id2) a1 (id1) a0 (id0) i/o 0 (lad0) i/o 1 (lad1) i/o 2 (lad2) vss (vss) i/o 3 (lad3) i/o 4 (res) i/o 5 (res) i/o 6 (res) i/o 7 (res) vdd (vdd) we# (lframe#) oe# (init#) nc nc figure 2: pin assignments for 32-lead tsop (*) designates lpc mode
a49lf040 preliminary (august, 2004, version 0.1) 3 amic technology, corp. block diagram high voltage generator data latch lpc mode interface lad[3:0] lclk lframe# id[3:0] gpi[4:0] a/a mux mode interface a[10:0] i/o 7 ~ i/o 0 we# oe# r/c# mode rst# address latch x-decoder y-decoder cell matrix y-gating control logic input/output buffers tbl# wp# init# rb#
a49lf040 preliminary (august, 2004, version 0.1) 4 amic technology, corp. table 1: pin description 1. in=input, out=output, i/o=input/output, pwr=power interface symbol pin name type a/a mux lpc descriptions a 10 -a 0 address in x inputs for addresses during read a nd write operations in a/a mux mode. row and column addresses are latched by r/c# pin. i/o 7 -i/o 0 data i/o x to output data during read cycle and receive input data during write cycle in a/a mux mode. t he outputs are in tri-state when oe# is high. oe# output enable in x to control the data output buffers. we# write enable in x to control the write operations. mode interface configuration pin in x x to determine which interface is operational. when held high, a/a mux mode is enabled and when held low, lpc mode is enabled. this pin must be setup at power-up or before return from reset and not change during device operation. this pin is internally pulled down with a resistor between 20-100 k ?. init# initialize in x this is the second reset pin for in-system use. init# and rst# pins are internally combined and initialize a device reset when driven low. id[3:0] identification inputs in x these four pins are part of the mechanism that allows multiple lpc devices to be attached to the same bus. to identify the component, the correct strapping of these pins must be set. the boot device must have id[3:0]=0000 and it is recommended that all subsequent devices should us e sequential up-count strapping. these pins are internally pulled down with a resistor between 20- 100 k ?. gpi[4:0] general purpose inputs in x these individual inputs can be used for additional board flexibility. the state of these pins can be read immediately at boot, through lpc internal registers. these i nputs should be at their desired state before the start of the pci clock cycle during which the read is attempted, and should remain in place until the end of the read cycle. unused gpi pins must not be floated. tbl# top block lock in x to prevent any write operations to the boot block when driven low, regardless of the stat e of the block lock registers. when tbl# is high it disables hardware write prot ection for the top boot block. this pin cannot be left unconnected. lad[3:0] lpc i/os i/o x i/o communications in lpc mode. lclk clock in x to provide a clock input to the devic e. this pin is the same as that for the pci clock and adheres to the pci specifications. lframe# frame in x to indicate start of a data transfe r operation; also used to abort an lpc cycle in progress. rst# reset in x x to reset the operation of the device wp# write protect in x when low, prevents any write operat ions to all but the highest addressable block. when wp# is high it disables hardware write protection for these blocks. this pin cannot be left unconnected. r/c# row/column select in x this pin determines whether the address pins are pointing to the row addresses or the column addresses in a/a mux mode. rb# ready/busy# out x to determine if the device is busy in write operations. valid only in a/a mux mode. res reserved x reserved. these pins must be left unconnected. vdd power supply pwr x x to provide power supply (3.0-3.6volt). vss ground pwr x x circuit ground. all vss pins must be grounded. nc no connection x x unconnected pins.
a49lf040 preliminary (august, 2004, version 0.1) 5 amic technology, corp. absolute maximum ratings* temperature under bias . . . . . . . . . .. . . . -55 c to + 125 c storage temperature . . . . . . . . . . . . . . . . . -65 c to + 125 c d.c. voltage on any pins with respect to ground (1) . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . -0.5v to vdd + 0.5v package power dissipation capability (ta=25 c) . . . . . . . . . . . . . . . . . . . . . . . . ?. . . . . . -0.5v to vdd + 0.5v output short circuit current (2) . . . . . . . . . .. . . . . . . 50ma notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may undershoot vss to -2.0v for periods of up to 20ns. maximum dc voltage on input and i/o pins is vdd + 0.5v. during volt age transitions, input or i/o pins may overshoot to vdd + 2.0v for periods up to 20ns. 2. no more than one output is shorted at a time. duration of the short circuit should not be greater than one second. *comments stresses above those listed under "a bsolute maximum ratings" may cause permanent damage to this dev ice. these are stress ratings only. functional operation of this device at these or any other conditions above those indi cated in the operational sections of these specifications are not implied or intended. exposure to the absolute maximum rating conditions for ex tended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . ?.. . . . . . 0 c to +85 c vdd supply voltages vdd for all devices . . . . . . . . . . . . . . . . ?.. . +3.0v to +3.6v operating ranges define t hose limits between which the functionally of the device is guaranteed. mode selection the a49lf040 flash memory devices can operate in two distinct interface modes: t he low pin count interface (lpc) mode and the address/addr ess multiplexed (a/a mux) mode. the mode pin is used to set the interface mode selection. if the mode pin is set to logic high, the device is in a/a mux mode; while if the mode pin is set low, the device is in the lpc mode. the mode pin must be configured prior to device operation. the mode pin is internally pulled down if the pin is not connected. in lpc mode, the device is configured to interface with its host using intel?s low pin count proprietary protocol. communication between host and the a49lf040 occurs via the 4-bit i/o communication signals, lad[3:0] and the lfra me#. in a/a mux mode, the device is programmed via an 11-bit address a 10 -a 0 and an 8- bit data i/o 7 -i/o 0 parallel signals. the address inputs are multiplexed in row and column selected by control signal r/c# pin. the column addresses are mapped to the higher internal addresses, and the row addresses are mapped to the lower internal addresses. see the device memory maps in figure 3 for address assignment. lpc mode operation the lpc interface consists of four data signals (lad[3:0]), one control signal (lframe#) and a clock (lclk). the data signals, control signal and clock comply with pci specifications. oper ations such as memory read and memory write use intel lpc propriety protocol. jedec standard sdp (software data protection) byte-program and block-erase command sequences are incorporated into the lpc memory cycles. chip-erase command is only available in a/a mux mode. the addresses and data are transferred through lad[3:0] synchronized with the input clock lclk during a lpc memory cycle. the pulse of lframe# is inserted for at least one clock period to indicate the start of a lpc memory cycle. the address or data on lad[3:0] is latched on the rising edge of lclk. the device enters standby mode when lframe# is high and no internal operation is in progress. the device is in ready mode when lframe# is low and no activity is on the lpc bus. lpc read operation lpc read operations read from the memory cells or specific registers in the lpc device. a valid lpc read operation starts when lframe# is low as lclk rises and a start value ?0000b? is on lad[3:0] t hen the next nibble ?010x? is on lad[3:0]. addresses and data are transferred to and from the device decided by a series of ?fields?. field sequences and contents are strictly defined for lpc read operations. refer to table 2 for lpc read cycle definition. lpc write operation lpc write operations write to the lpc interface or lpc registers. a valid lpc write operation starts when lframe# is low as lclk rises and a start value ?0000b? is on lad[3:0] then the next nibbl e ?011x? is on lad[3:0]. addresses and data are transfe rred to and from the device decided by a series of ?fields?. field sequences and contents are strictly defined for lpc writ e operations. refer to table 3 for lpc write cycle definition. lpc abort operation if lframe# is driven low for one or more clock cycles during a lpc cycle, the cycle will be terminated and the device will wait for the abort command. the host may drive the lad[3:0] with ?1111b? (abort command) to return the device to ready mode. if abort occurs during a write operation such as checking the operation status with data# polling (i/o 7 ) or toggle bit (i/o 6 ) pins, the read status cycle will be aborted but the internal write operation will not be affected. in this case, only the reset operation initiated by rst# or init# pin can terminate the write operation.. response to invalid fields during lpc operations, the lpc will not explicitly indicate that it has received invalid fi eld sequences. the response to specific invalid fields or sequences is as follows: address out of range: the a49lf040 will only response to address range as specified in t able 4. address a22 has the special function of directing reads and writes to the flash memory (a22=1) or to the register space (a22=0).
a49lf040 preliminary (august, 2004, version 0.1) 6 amic technology, corp. table 2: lpc read cycle 1. field contents are valid on the risi ng edge of the present clock cycle. lpc single-byte read waveforms lclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 start address tar0 tar1 sync data tar0 tar1 lframe# lad[3:0] cyctype + dir clock cycle field name field contents lad[3:0] 1 lad[3:0] direction comments 1 start 0000 in lframe# must be active (low) for the part to respond. only the last start field (before lframe# transit ioning high) should be recognized. 2 cyctype + dir 010x in indicates the type of cycle. bits 3: 2 must be ?01b? for memory cycle. bit 1 indicates the type of transfer ?0? for read. bit 0 is reserved. 3-10 address yyyy in address phase for memory cycle. lpc protocol supports a 32-bit address phase. yyyy is one nibble of the entire address. addresses are transferred most-significant nibble first. see table 4 for address bits definition and table 5 for valid memory address range. 11 tar0 1111 in then float in this clock cycle, the host has driven the bus to all 1s and then floats the bus. this is the first part of the bus ?turnaround cycle.? 12 tar1 1111(float) float then out the a49lf040 takes control of the bus during this cycle. 13 sync 0000 out the a49lf040 outputs the value 0000b indicating that data will be available during the next clock cycle. 14 data zzzz out this field is the least-significant nibble of the data byte. 15 data zzzz out this field is the most-significant nibble of the data byte. 16 tar0 1111 in then float in this clock, the host has driven t he bus to all 1s and then floats the bus. this is the first part of the bus ?turnaround cycle.? 17 tar1 1111(float) float then out the a49lf040 takes control of the bus during this cycle.
a49lf040 preliminary (august, 2004, version 0.1) 7 amic technology, corp. table 3: lpc write cycle 1. field contents are valid on the risi ng edge of the present clock cycle. lpc write waveforms lclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 start address tar0 tar1 sync data tar0 tar1 lframe# lad[3:0] cyctype + dir clock cycle field name field contents lad[3:0] 1 lad[3:0] direction comments 1 start 0000 in lframe# must be active (low) for the part to respond. only the last start field (before lframe# transitioning high) should be recognized. 2 cyctype + dir 010x in indicates the type of cycle. bits 3: 2 must be ?01b? for memory cycle. bit 1 indicates the type of transfer ?1? for write. bit 0 is reserved. 3-10 address yyyy in address phase for memory cycle. lpc protocol supports a 32-bit address phase. yyyy is one nibble of the entire address. addresses are transferred most-significant nibble first. see table 4 for address bits definition and table 5 for valid memory address range. 11 data zzzz in this field is the least-significant nibble of the data byte. 12 data zzzz in this field is the most-significant nibble of the data byte. 13 tar0 1111 in then float in this clock cycle, the host has driven the bus to all ?1?s and then floats the bus. this is the first part of the bus ?turnaround cycle.? 14 tar1 1111(float) float then out the a49lf040 takes control of the bus during this cycle. 15 sync 0000 out the a49lf040 outputs the values 0000, indicating that it has received data or a flash command. 16 tar0 1111 out then float in this clock cycle, the a49lf040 has driven the bus to all ?1?s and then floats the bus. this is the fi rst part of the bus ?turnaround cycle.? 17 tar1 1111(float) float then in host resumes control of the bus during this cycle.
a49lf040 preliminary (august, 2004, version 0.1) 8 amic technology, corp. id mismatch: the a49lf040 will compare id bits in the address field with the hardware id strapping. if there is a mismatch, the device will ignore the cycle. refer to table 6 multiple device selection configuration for detail. device memory hardware write protection the top boot lock (tbl#) and write protect (wp#) pins are provided for hardware write protection of device memory in the a49lf040. the tbl# pin is used to write protect the top boot block (64 kbytes) at the highest flash memory address range for the a49lf040. wp# pin write protects the remaining blocks in the flash memory. an active low signal at the tbl# pin prevents program and erase operations of the top boot block. the wp# pin serves the same function for the remaining blocks of the device memory. the tbl# and wp# pins write protection functi ons operate inde pendently of one another. both tbl# and wp# pins must be set to their required protection states prior to starting a program or erase operation. a logic level change occurring at the tbl# or wp# pin during a program or erase operation could cause unpredictable results. tbl# and wp# pins cannot be left unconnected. clearing the write-lock bit in any register when wp# is low will have no functional effect, even though the register may indicate that the block is no longer locked. reset a v il on init# or rst# pin initiates a device reset. init# and rst# pins have the same function internally. it is required to drive init# or rst# pins low during a system reset to ensure proper cpu initialization. du ring a read operation, driving init# or rst# pins low deselects the device and places the output drivers, lad[3:0], in a high-impedance state. the reset signal must be held low for a minimal duration of time t rstp . a reset latency will occur if a reset procedure is performed during a program or erase operation. see table 19, reset timing parameters fo r more information. a device reset during an active program or erase will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete erase or program operation. in this case, the device can take up to t rste to abort a program or erase operation. write operation status detection the a49lf040 device provides two software means to detect the completion of a write (progr am or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (i/o 7 ) and toggle bit (i/o 6 ). the end-of-write detection mode is incorporated into the lpc read cycle. the actual completion of the nonvolatile write is as ynchronous with the system; therefore, either a data# po lling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either i/o 7 or i/o 6 . in order to prevent spurious reje ction, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling (i/o 7 ) when the a49lf040 device is in the internal program operation, any attempt to read i/o 7 will produce the complement of the true data. once the program operation is completed, i/o 7 will produce true data. note that even though i/o 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase operation, any attempt to read i/o 7 will produce a ?0?. once the internal erase operation is completed, i/o 7 will produce a ?1?. proper status will not be given using data# polling if the address is in the invalid range. toggle bit (i/o 6 ) during the internal program or erase operation, any consecutive attempts to read i/o 6 will produce alternating ?0?s and ?1?s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. multiple device selection the four id pins, id[3:0], allow multiple devices to be attached to the same bus by using different id strapping in a system. when the a49lf040 is us ed as a boot device, id[3:0] must be strapped as 0000, all subsequent devices should use a sequential up-count str apping (i.e. 0001, 0010, 0011, etc.). the id bits in the add ress field are inverse of the hardware strapping. the address bits [a23, a21:a19] for a49lf004 are used to select the device with proper ids. see table 6 for ids. the a49lf040 will compare the strapping values, if there is a mismatch, the device will ignore the remainder of the cycle and go into standby mode. since there is no id support in a/a mux mode, to program multiple devices a stand-alone prom programmer is recommended. registers there are two types of registers available on the a49lf040, the general purpose inputs r egister, and the jedec id registers. these registers appear at their respective address location in the 4 gbyte system memory map. unused register locations will read as 00h. any attempt to read or write any register during an internal wr ite operation will be ignored. refer to table 7 for the lpc register memory map. general purpose inputs register the gpi_reg (general purpose inputs register) passes the state of gpi[4:0] pins at power-up on the a49lf040. it is recommended that the gpi[4:0] pins be in the desired state before lframe# is brought low fo r the beginning of the next bus cycle, and remain in that state until the end of the cycle. there is no default value since this is a pass-through register. see table 8 for the gpi_reg bits and function, and table 9 for memory address locations for its respective device strapping.
a49lf040 preliminary (august, 2004, version 0.1) 9 amic technology, corp. table 4: address bit definition table 5: address decoding range table 6: multiple device selection configuration table 7: lpc register memory map a 31 :a 23 a 23 a 22 a 21 :a 19 a 18 :a 0 1111 1111b id[3] 1 = memory access 0 = register access id[2:0] device memory address id strapping device access a 21 :a 19 memory size memory access ffff ffffh: ffc0 0000h 4 mbyte device #0 ? 7 register access ffbf ffffh: ff80 0000h 4 mbyte memory access ff7f ffffh: ff40 0000h 4 mbyte device #8 - 15 register access ff3f ffffh: ff00 0000h 4 mbyte address bits decoding device# hardware strapping id[3:0] a23 a21 a20 a19 0 (boot device) 0000 1 1 1 1 1 0001 1 1 1 0 2 0010 1 1 0 1 3 0011 1 1 0 0 4 0100 1 0 1 1 5 0101 1 0 1 0 6 0110 1 0 0 1 7 0111 1 0 0 0 8 1000 0 1 1 1 9 1001 0 1 1 0 10 1010 0 1 0 1 11 1011 0 1 0 0 12 1100 0 0 1 1 13 1101 0 0 1 0 14 1110 0 0 0 1 15 1111 0 0 0 0 memory address mnemonic register name default type ffbc0100h gpi_reg lpc general pu rpose input register n/a r ffbc0000h manuf_reg manufacturer id register 37h r ffbc0001h dev_reg device id register 9dh r ffbc0003h cont_reg continuat ion id register 7fh r
a49lf040 preliminary (august, 2004, version 0.1) 10 amic technology, corp. jedec id registers the jedec id registers identify the device as a49lf040 and manufacturer as sst in lpc mode. see table 9 for memory address locations for its resp ective jedec id location. table 8: general purpose inputs register pin number bit bit function 32-plcc 32-tsop 7:5 - reserved - - 4 gpi[4] gpi_reg bit 4 30 6 3 gpi[3] gpi_reg bit 3 3 11 2 gpi[2] gpi_reg bit 2 4 12 1 gpi[1] gpi_reg bit 1 5 13 0 gpi[0] gpi_reg bit 0 6 14 table 9 memory map register addresses for a49lf040 jedec id device# hardware strapping id[3:0] gpi_reg manufacturer continuation device 0 (boot device) 0000 ffbc 0100h ffbc 0000h ffbc 0003h ffbc 0001h 1 0001 ffb4 0100h ffb4 0000h ffb4 0003h ffb4 0001h 2 0010 ffac 0100h ffac 0000h ffac 0003h ffac 0001h 3 0011 ffa4 0100h ffa4 0000h ffa4 0003h ffa4 0001h 4 0100 ff9c 0100h ff9c 0000h ff9c 0003h ff9c 0001h 5 0101 ff94 0100h ff94 0000h ff94 0003h ff94 0001h 6 0110 ff8c 0100h ff8c 0000h ff8c 0003h ff8c 0001h 7 0111 ff84 0100h ff84 0000h ff84 0003h ff84 0001h 8 1000 ff3c 0100h ff3c 0000h ff3c 0003h ff3c 0001h 9 1001 ff34 0100h ff34 0000h ff34 0003h ff34 0001h 10 1010 ff2c 0100h ff2c 0000h ff2c 0003h ff2c 0001h 11 1011 ff24 0100h ff24 0000h ff24 0003h ff24 0001h 12 1100 ff1c 0100h ff1c 0000h ff1c 0003h ff1c 0001h 13 1101 ff14 0100h ff14 0000h ff14 0003h ff14 0001h 14 1110 ff0c 0100h ff0c 0000h ff0c 0003h ff0c 0001h 15 1111 ff04 0100h ff04 0000h ff04 0003h ff04 0001h
a49lf040 preliminary (august, 2004, version 0.1) 11 amic technology, corp. address/address multiplexed (a/a mux) mode device operation commands are used to initiate the memory operation functions of the device. the data portion of the software command sequence is latched on the rising edge of we#. during the software command sequence the row address is latched on the falling edge of r/c# and the column address is latched on the rising edge of r/c#. refer to table 8 and table 9 for operation modes and the command sequence. read the read operation of the a49lf 040 device is controlled by oe#. oe# is the output contro l and is used to gate data from the output pins. refer to the read cycle timing diagram, figure 10 for further details. reset a v il on rst# pin initiates a device reset. byte-program operation the a49lf040 device is programmed on a byte-by-byte basis. before programming, one mu st ensure that the block, in which the byte which is being programmed exists, is fully erased. the byte-program operat ion is initiated by executing a four-byte command load sequence for software data protection with address and data in the last byte sequence. during the byte-program oper ation, the row address (a10-a0) is latched on the falling edge of r/c# and the column address (a18-a11) is latched on the rising edge of r/c#. the data bus is latched in the risi ng edge of we#. see figure 11 for program operation timing diagram, figure 14 for timing waveforms, and figure 19 for its flowchart. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands written during the internal program operation will be ignored. table 10: a/a mux mode operation selection block-erase operation the block-erase operation allows the system to erase the device in 64 kbyte uniform block size for the a49lf040. the block-erase operation is initia ted by executing a six-byte command load sequence for software data protection with block-erase command (30h or 50h) and block address. the internal block-erase operation begins after the sixth we# pulse. the end-of-erase can be determined using either data# polling or toggle bit methods. see figure 15 for timing waveforms. any commands written during the block- erase operation will be ignored. chip-erase the a49lf040 device provides a chip-erase operation only in a/a mux mode, which allows the user to erase the entire memory array to the ?1?s state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six-byte software data protection command sequence with chip-erase command (10h) with address 5555h in the last byte sequence. the internal erase operation begins with the risi ng edge of the sixth we#. during the internal erase oper ation, the only valid read is toggle bit or data# polling. see table 11 for the command sequence, figure 16 for timing diagram, and figure 21 for the flowchart. any commands written during the chip-erase operation will be ignored. write operation status detection the a49lf040 device provides two software means to detect the completion of a write cycl e, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (i/o 7 ) and toggle bit (i/o 6 ). the end-of-write detection mode is enabled after the rising edge of we# which initiates the in ternal write operation. the actual completion of the nonvolatile write is asynchronous with the system; therefore, ei ther a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either i/o 7 or i/o 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling (i/o 7 ) when the a49lf040 device is in the internal program operation, any attempt to read i/o 7 will produce the complement of the true data. once the program operation is completed, i/o 7 will produce true data. note that even though i/o 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase operation, any attempt mode rst# oe# we# address i/o read v ih v il v ih a in d out write v ih v ih v il a in d in standby v ih v ih v ih x high z output disable v ih v ih x x high z reset v il x x x high z a18 ? a2 = x, a1 = v il , a0 = v il manufacturer id a18 ? a2 = x, a1 = v il , a0 = v ih device id product identification v ih v il v ih a18 ? a2 = x, a1 = v ih , a0 = v ih continuation id
a49lf040 preliminary (august, 2004, version 0.1) 12 amic technology, corp. to read i/o 7 will produce a ?0?. once the internal erase operation is completed, i/o 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# pulse for program operation. for block- or chip-erase, the data# polling is valid after the rising edge of sixth we# pulse. see figure 12 for data# polling timing diagram. proper status will not be given using data# polli ng if the address is in the invalid range. toggle bit (i/o 6 ) during the internal program or erase operation, any consecutive attempts to read i/o 6 will produce alternating ?0?s and ?1?s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the device is then ready for the next operation. the toggle bit is valid after the rising edge of fourth we# pulse for program operation. for block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# pulse. see figure 13 for toggle bit timing diagram. data protection the a49lf040 device provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, we# high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down. software data protection (sdp) the a49lf040 provides the jedec approved software data protection scheme for all data alteration operation, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequences. the three-byte load sequence is used to init iate the program operation, providing optimal protecti on from inadvertent write operations, e.g., during the syst em power-up or power-down. any erase operation requires the inclusion of a six-byte load sequence. the a49lf040 device is shipped with the software data protection permanently enabled. see table 11 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode, within t rc . electrical specifications the ac and dc specifications fo r the lpc interface signals (lad[3:0], lclk, lframe#, and rst#) as defined in section 4.2.2 of the pci local bus specification, rev. 2.1 . refer to table 12 for the dc voltage and current specifications. refer to the s pecifications on table 13 to table 22 for clock, read/write, and reset operations. product identification the product identification mode identifies the manufacturer id, continuation id, and device id of the a49lf040. see table 9 for detail information.
a49lf040 preliminary (august, 2004, version 0.1) 13 amic technology, corp. figure 3: system memory map an d device memory map for a49lf040 block 7 (64k bytes) 000000 00ffff 010000 01ffff 020000 02ffff 030000 03ffff 040000 04ffff 050000 05ffff 060000 06ffff 070000 07ffff block 6 (64k bytes) block 5 (64k bytes) block 4 (64k bytes) block 3 (64k bytes) block 2 (64k bytes) block 1 (64k bytes) block 0 (64k bytes) tbl# device memory wp# for block 6 ~ 0 a49lf040 table 11: software data protection command definition notes: 1. lpc mode uses consecutive write cycles to complete a command sequence; a/a mux mode us es consecutive bus cycles to complete a command sequence. 2. yyyy = a[31:16]. in lpc mode, during sdp command sequence, yyyy must be within memory address range specified in table 5. in a/a mux mode, yyyy can be v il or v ih , but no other value. 3. chip erase is available in a/a mux mode only. 4. ba: block erase address. 5. either 30h or 50h are acceptable for block erase. 6. pa: program byte address; pd: byte data to be programmed. 7. both product id exit commands are equivalent. 1 st cycle (1) 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle command bus cycles addr (2) data addr data addr data addr data addr data addr data block erase 6 yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 80h yyyy 5555h aah yyyy 2aaah 55h ba (4) 30h/50h (5) chip erase (3) 6 yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 80h yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 10h byte program 4 yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h a0h pa (6) pd (6) product id entry 3 yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 90h product id exit (7) 1 xxxx xxxxh f0h product id exit (7) 3 yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h f0h
a49lf040 preliminary (august, 2004, version 0.1) 14 amic technology, corp. operating range ac conditions of test table 12: dc operating char acteristics (all interfaces) notes: 1. i dd active while erase or program is in progress. 2. the device is in ready mode when no activity is on the lpc bus. 3. do not violate processor or chipse t specification regarding init# voltage. table 13: recommended system power-up timings symbol parameter min units t pu-read (1) power-up to read operation 100 s t pu-write (1) power-up to write operation 100 s notes: 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this parameter . range ambient temperature v dd commercial 0 c to +85 c 3.0-3.6v input rise/fall time . . . . . . . . . . . . . . . . . . . . . . 3ns output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . cl = 30pf limits symbol parameter min max units test conditions active v dd current: read 12 ma i dd active v dd current: write (1) 24 ma address input=v il /v ih , at f=1/t rc min, v dd =v dd max(a/a mux mode) oe#=v ih , we#=v ih i sb standby v dd current (lpc mode) 100 a lframe#=0.9v dd ,f=33mhz,v dd =v dd max, all other inputs 0.9v dd or 0.1v dd i ry (2) ready mode v dd current (lpc mode) 10 ma lframe#=v il ,f=33mhz,v dd =v dd max, all other inputs 0.9v dd or 0.1v dd i i input current for mode and id[3:0] pins 100 a v in =gnd to v dd , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v ihi (3) init# input high voltage 1.0 v dd +0.5 v v dd =v dd max v ili (3) init# input low voltage -0.5 0.4 v v dd =v dd min v ih input high voltage 0.5v dd v dd +0.5 v v dd =v dd max v il input low voltage -0.5 0.3v dd v v dd =v dd min v ol output low voltage 0.1v dd v iol=1500 a, v dd =v dd min v oh output high voltage 0.9v dd v ioh=-500 a, v dd =v dd min
a49lf040 preliminary (august, 2004, version 0.1) 15 amic technology, corp. table 14: pin impedance (v dd =3.3v, ta=25 c, f=1mhz, other pins open) parameter description test condition max c i/o (1) i/o pin capacitance v i/o = 0v 12pf c in (1) input capacitance v in = 0v 12pf l pin (2) pin inductance 20nh notes: 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. refer to pci specifications. table 15: clock timing parameters symbol parameter min max units t cyc lclk cycle time 30 ns t high lclk high time 11 ns t low lclk low time 11 ns lclk slew rate (peak-to-peak) 1 4 v/ns figure 4: lclk waveform 0.2 v dd 0.5 v dd 0.4 v dd 0.3 v dd 0.6 v dd 0.4 v dd peak-to-peak (min) t cyc t low t high table 16: lpc mode read/write cycle timing parameters, v dd =3.0-3.6v symbol parameter min max units t su input set up time to lclk rising 7 ns t dh lclk rising to data hold time 0 ns t val lclk rising to data valid 2 11 ns t on lclk rising to active (float to active delay) 2 ns t off lclk rising to inactive (active to float delay) 28 ns
a49lf040 preliminary (august, 2004, version 0.1) 16 amic technology, corp. table 17: lpc mode interface measurement condition parameters symbol value units v th 0.6 v dd v v tl 0.2 v dd v v test 0.4 v dd v v max 0.4 v dd v input signal edge rate 1v/ns figure 5: input timing parameters v tl v th t su v test lclk lad[3:0] (valid input data) v max valid inputs t dh figure 6: output timing parameters v tl v th t on t off t val v test lclk lad[3:0] (valid output data) lad[3:0] (float output data)
a49lf040 preliminary (august, 2004, version 0.1) 17 amic technology, corp. table 18: lpc mode interface ac input/output characteristics symbol parameter test conditions min max units 0 < v out 0.3v dd -12 v dd ma 0.3v dd < v out 0.9v dd -17.1(v dd -v out ) ma i oh (ac) switching current high 0.7v dd < v out v dd equation c ma (test point) v out = 0.7v dd -32 v dd ma v dd > v out 0.6v dd 16v dd ma 0.6v dd > v out > 0.1v dd 26.7v out ma i ol (ac) switching current low 0.18v dd > v out > 0 equation d ma (test point) v out =0.18v dd 38v dd ma i cl low clamp current -3 < v in -1 -25+(v in +1)/0.015 ma i ch high clamp current v dd +4 > v in > v dd +1 25+(v in -v dd -1)/0.015 ma slewr output rise slew rate 0.2v dd -0.6v dd load 1 4 v/ns slewf output fall slew rate 0.6v dd -0.2v dd load 1 4 v/ns notes: 1. see pci specification. 2. pci specification output load is used. table 19: lpc mode interface reset timing parameters, v dd =3.0-3.6v symbol parameter min max units t prst v dd stable to reset low 1 ms t krst clock stable to reset low 100 s t rstp rst# pulse width 100 ns t rstf rst# low to output float 48 ns t rst (1) rst# high to lframe# low 1 s t rste rst# low to reset during erase or program 10 s rst# or init# slew rate 50 mv/ns notes: 1. there will be a latency of t rste if a reset procedure is performed dur ing a program or erase operation. figure 7: reset timing diagram t krst t prst t rst t rstf t rste t rstp program or erase operation aborted v dd lclk rst#/init# lad[3:0] lframe#
a49lf040 preliminary (august, 2004, version 0.1) 18 amic technology, corp. figure 8: a/a mux mode ac input/output reference waveforms v it v ot reference points input output v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic high and v ilt (0.1v dd ) for a logic low. measurement reference points for inputs and outputs are v it (0.5v dd ) and v ot (0.5v dd ). input rise and fall times (10% <-> 90%) are < 5ns note: v it : v input test v ot : v output test v iht : v input high test v ilt : v input low test figure 9: a/a mux mode test load condition cl=30pf to tester to dut
a49lf040 preliminary (august, 2004, version 0.1) 19 amic technology, corp. a/a mux mode ac characteristics table 20: read cycle timing parameters v dd =3.0-3.6v symbol parameter min max units t rc read cycle time 270 ns t rst rst# high to row address setup 1 s t as r/c# address set-up time 45 ns t ah r/c# address hold time 45 ns t aa address access time 120 ns t oe output enable access time 60 ns t olz oe# low to active output 0 ns t ohz oe# high to high-z output 35 ns t oh output hold from address change 0 ns table 21: program/erase cycle timing parameters, v dd =3.0-3.6v symbol parameter min max units t rst rst# high to row address setup 1 s t as r/c# address setup time 50 ns t ah r/c# address hold time 50 ns t cwh r/c# to write enable high time 50 ns t oes oe# high setup time 20 ns t oeh oe# high hold time 20 ns t oep oe# to data# polling delay 40 ns t oet oe# to toggle bit delay 40 ns t wp we# pulse width 100 ns t wph we# pulse width high 100 ns t ds data setup time 50 ns t dh data hold time 5 ns t ida product id access and exit time 150 ns t bp byte programming time 300 s t be block erase time 8 s t sce chip erase time 10 s table 22: reset timing parameters, v dd =3.0-3.6v symbol parameter min max units t prst v dd stable to reset low 1 ms t rstp rst# pulse width 100 ns t rstf rst# low to output float 48 ns t rst (1) rst# high to lframe# low 1 s t rste rst# low to reset during erase or program 10 s 1. there will be a reset latency of trste if a reset pr ocedure is performed during a pr ogram or erase operation.
a49lf040 preliminary (august, 2004, version 0.1) 20 amic technology, corp. figure 10: a/a mux mode read cycle timing diagram t rst rst# address we# oe# i/o 7 -i/o 0 t rstp row address column address row address column address t rc t as t ah t as t ah v ih t oe t aa t ohz t oh t olz data valid high-z high-z r/c# figure 11: a/a mux mode write cycle timing diagram t rst rst# address oe# we# i/o 7 -i/o 0 t rstp row address column address t as t ah t as t ah t ds t wp data valid high-z r/c# t oes t wph t dh t oeh t cwh
a49lf040 preliminary (august, 2004, version 0.1) 21 amic technology, corp. figure 12: a/a mux mode data# polling timing diagram address we# oe# i/o 7 row address column address high-z r/c# write operation complete data in write operation in progress final input command status bit data t oep command input row address column address row address column address row address column address data# data# data status bit figure 13: a/a mux mode toggle bit timing diagram address we# oe# i/o 6 row address column address high-z r/c# write operation complete data in write operation in progress final input command status bit data t oet command input row address column address row address column address row address column address data status bit
a49lf040 preliminary (august, 2004, version 0.1) 22 amic technology, corp. figure 14: a/a mux mode byte program timing diagram address oe# we# i/o 7 -i/o 0 high-z r/c# aa byte program operation in progress t wp byte program command input 55 a0 pd t wph t bp 5555 2aaa 5555 pa pa = byte program address pd = byte program data four-byte byte program command sequence figure 15: a/a mux mode block erase timing diagram address oe# we# i/o 7 -i/o 0 high-z r/c# aa block erase operation in progress t wp block erase command input t wph 5555 2aaa 5555 5555 ba = block address six-byte block erase command sequence 55 80 aa 55 30/50 2aaa ba t be
a49lf040 preliminary (august, 2004, version 0.1) 23 amic technology, corp. figure 16: a/a mux mode chip erase timing diagram address oe# we# i/o 7 -i/o 0 high-z r/c# aa chip erase operation in progress t wp chip erase command input t wph 5555 2aaa 5555 5555 six-byte chip erase command sequence 55 80 aa 55 10 2aaa 5555 t sce figure 17: a/a mux mode product id entry and read timing diagram address oe# we# i/o 7 -i/o 0 high-z r/c# aa t wp t wph 5555 2aaa 5555 three-byte product id entry command sequence 55 90 37 95 7f 0000 0001 0003 t aa t ida figure 18: a/a mux mode product id exit and reset timing diagram address oe# we# i/o 7 -i/o 0 high-z r/c# aa t wp t wph 5555 2aaa 5555 three-byte product id exit and reset command sequence 55 f0
a49lf040 preliminary (august, 2004, version 0.1) 24 amic technology, corp. figure 19: automatic byte program algorithm start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: a0h write command address: pa data: pd i/o 7 = data ? or i/o 6 stop toggle? byte program completed no yes pa: byte program address pd: byte program data
a49lf040 preliminary (august, 2004, version 0.1) 25 amic technology, corp. figure 20: automatic block erase algorithm start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: 80h write command address: 5555h data: aah i/o 7 = data ? or i/o 6 stop toggle? block erase completed no yes ba: block address write command address: 2aaah data: 55h write command address: ba data: 30h or 50h
a49lf040 preliminary (august, 2004, version 0.1) 26 amic technology, corp. figure 21: automatic chip erase algorithm start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: 80h write command address: 5555h data: aah i/o 7 = data ? or i/o 6 stop toggle? chip erase completed no yes write command address: 2aaah data: 55h write command address: 5555h data: 10h
a49lf040 preliminary (august, 2004, version 0.1) 27 amic technology, corp. figure 22: product id command flowchart start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: 90h enter product id mode start write command address: 5555h data: aah write command address: 2aaah data: 55h write command address: 5555h data: f0h exit product id mode write command address: xxxxh data: f0h or
a49lf040 preliminary (august, 2004, version 0.1) 28 amic technology, corp. ordering information a49lf040t x - 33 c temperature range c = commercial (0 c to +85 c) clock frequency 33 = 33mhz package type l = plcc x = tsop (8mmx14mm) device number 4 mbit lpc flash memory part no. clock frequency (mhz) boot block location temperature range package type a49lf040tl-33 top 0 c to +85 c 32-pin plcc A49LF040TL-33F top 0 c to +85 c 32-pin pb-free plcc a49lf040tx-33 top 0 c to +85 c 32-pin tsop (8mm x 14 mm) a49lf040tx-33f 33 top 0 c to +85 c 32-pin pb-free tsop (8mm x 14 mm)
a49lf040 preliminary (august, 2004, version 0.1) 29 amic technology, corp. package information plcc 32l outline dimension unit: inches/mm a 1 a 2 a e d y h d d 13 g d b 1 b g e c 5 14 20 21 29 30 32 1 4 e h e l dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.134 - - 3.40 a 1 0.0185 - - 0.47 - - a 2 0.105 0.110 0.115 2.67 2.80 2.93 b 1 0.026 0.028 0.032 0.66 0.71 0.81 b 0.016 0.018 0.021 0.41 0.46 0.54 c 0.008 0.010 0.014 0.20 0.254 0.35 d 0.547 0.550 0.553 13.89 13.97 14.05 e 0.447 0.450 0.453 11.35 11.43 11.51 e 0.044 0.050 0.056 1.12 1.27 1.42 g d 0.490 0.510 0.530 12.45 12.95 13.46 g e 0.390 0.410 0.430 9.91 10.41 10.92 h d 0.585 0.590 0.595 14.86 14.99 15.11 h e 0.485 0.490 0.495 12.32 12.45 12.57 l 0.075 0.090 0.095 1.91 2.29 2.41 y - - 0.003 - - 0.075 0 - 10 0 - 10 notes: 1. dimensions d and e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only.
a49lf040 preliminary (august, 2004, version 0.1) 30 amic technology, corp. package information tsop 32l type i (8 x 14mm) outline dimensions unit: inches/mm e detail "a" detail "a" b d 1 e d l a a 2 c a 1 pin1 gage plane 0.254 d y dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.0067 0.0087 0.0106 0.17 0.22 0.27 c 0.004 - 0.0083 0.10 - 0.21 e 0.311 0.315 0.319 7.90 8.00 8.10 e - 0.0197 - - 0.50 - d 0.543 0.551 0.559 13.80 14.00 14.20 d 1 0.484 0.488 0.492 12.30 12.40 12.50 l 0.020 0.024 0.028 0.50 0.60 0.70 y 0.000 - 0.003 0.00 - 0.076 0 3 5 0 3 5 notes: 1. dimension e does not include mold flash. 2. dimension d 1 does not include interlead flash. 2. dimension b does not include dambar protrusion.

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